? semiconductor components industries, llc, 2006 april, 2006 ? rev. 6 1 publication order number: nlas325/d nlas325 dual spst analog switch, low voltage, single supply the nlas325 is a dual spst (single pole, single throw) switch, similar to 1/2 a standard 4066. the device permits the independent selection of 2 analog/digital signals. available in the ultra?small 8 package. the use of advanced 0.6 cmos process, improves the r on resistance considerably compared to older higher voltage technologies. features ? on resistance is 20 typical at 5.0 v ? matching is < 1.0 between sections ? 2.0?6.0 v operating range ? ultra low < 5.0 pc charge injection ? ultra low leakage < 1.0 na at 5.0 v, 25 c ? wide bandwidth > 200 mhz, ?3.0 db ? 2000 v esd (hbm) ? r on flatness 6.0 at 5.0 v ? us8 package ? independent enables; one positive, one negative ? pb?free package is available v cc no1 com1 gnd in2 nc2 1 2 3 8 7 6 com2 in1 45 figure 1. pinout see detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. ordering information marking diagram pin assignment 1 2 3 in2 no1 gnd 4 5 com1 in1 6 function table l h on/off enable input analog switch 1 off on 7 8 v cc com2 nc2 us8 us suffix case 493 8 1 a9 = device code m = date code* = pb?free package analog switch 2 on off http://onsemi.com 1 8 a9 m (note: microdot may be in either location) *date code orientation may vary depending upon manufacturing location.
nlas325 http://onsemi.com 2 maximum ratings symbol parameter value unit v cc dc supply voltage 0.5 to 7.0 v v i dc input voltage 0.5 to 7.0 v v o dc output voltage 0.5 to 7.0 v i ik dc input diode current v i < gnd 50 ma i ok dc output diode current v o < gnd 50 ma i o dc output sink current 50 ma i cc dc supply current per supply pin 100 ma i gnd dc ground current per ground pin 100 ma t stg storage temperature range 65 to 150 c t l lead temperature, 1.0 mm from case for 10 seconds 260 c t j junction temperature under bias 150 c ja thermal resistance (note 1) 250 c/w p d power dissipation in still air at 85 c 250 mw msl moisture sensitivity level 1 f r flammability rating oxygen index: 28 to 34 ul 94 v?0 @ 0.125 in v esd esd withstand voltage human body model (note 2) machine model (note 3) charged device model (note 4) > 2000 > 200 n/a v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. measured with minimum pad spacing on an fr4 board, using 10 mm?by?1 inch, 2?ounce copper trace with no air flow. 2. tested to eia/jesd22?a114?a. 3. tested to eia/jesd22?a115?a. 4. tested to jesd22?c101?a. recommended operating conditions symbol parameter min max unit v cc dc supply voltage 2.0 5.5 v v in digital select input voltage gnd 5.5 v v is analog input voltage (nc, no, com) gnd v cc v t a operating temperature range 55 125 c t r , t f input rise or fall time, select v cc = 3.3 v 0.3 v v cc = 5.0 v 0.5 v 0 0 100 20 ns/v device junction temperature versus time to 0.1% bond failures junction temperature c time, hours time, years 80 1,032,200 117.8 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 normalized failure rate 1 1 10 100 1000 failure rate of plastic = ceramic until intermetallics occur figure 2. failure rate vs. time junction temperature time, years t j = 130 c t j = 120 c t j = 110 c t j = 100 c t j = 90 c t j = 80 c
nlas325 http://onsemi.com 3 dc characteristics ? digital section (voltages referenced to gnd) guaranteed limit symbol parameter condition v cc 55 c to 25 c 85 c 125 c unit v ih minimum high?level input voltage, select inputs 2.0 2.5 3.0 4.5 5.5 1.5 1.9 2.1 3.15 3.85 1.5 1.9 2.1 3.15 3.85 1.5 1.9 2.1 3.15 3.85 v v il maximum low?level input voltage, select inputs 2.0 2.5 3.0 4.5 5.5 0.5 0.6 0.9 1.35 1.65 0.5 0.6 0.9 1.35 1.65 0.5 0.6 0.9 1.35 1.65 v i in maximum input leakage current, select inputs v in = 5.5 v or gnd 0 v to 5.5 v 0.2 2.0 2.0 a i cc maximum quiescent supply current select and v is = v cc or gnd 5.5 4.0 4.0 8.0 a dc electrical characteristics ? analog section guaranteed limit symbol parameter condition v cc 55 c to 25 c 85 c 125 c unit r on maximum ?on? resistance (figures 16 ? 22) v in = v il or v ih v is = gnd to v cc i in i 10 ma 2.5 3.0 4.5 5.5 85 45 30 25 95 50 35 30 105 55 40 35 r flat(on) on resistance flatness (figures 16 ? 22) v in = v il or v ih i in i 10 ma v is = 1.0 v, 2.0 v, 3.5 v 4.5 4.0 4.0 5.0 i nc(off) i no(off) no or nc off leakage current (figure 8) v in = v il or v ih v no or v nc = 1.0 v com 4.5 v 5.5 1.0 10 100 na i com(on) com on leakage current (figure 8) v in = v il or v ih v no 1.0 v or 4.5 v with v nc floating or v no 1.0 v or 4.5 v with v no floating v com = 1.0 v or 4.5 v 5.5 1.0 10 100 na
nlas325 http://onsemi.com 4 ac electrical characteristics (input t r = t f = 3.0 ns) guaranteed maximum limit v cc v is 55 c to 25 c 85 c 125 c symbol parameter test conditions (v) (v) min typ* max min max min max unit t on turn?on time (figures 11 and 12) r l = 300 c l = 35 pf (figures 4 and 5) 2.5 3.0 4.5 5.5 2.0 2.0 3.0 3.0 5.0 5.0 2.0 2.0 23 16 11 9.0 35 24 16 14 5.0 5.0 2.0 2.0 38 27 19 17 5.0 5.0 2.0 2.0 41 30 22 20 ns t off turn?off time (figures 11 and 12) r l = 300 c l = 35 pf (figures 4 and 5) 2.5 3.0 4.5 5.5 2.0 2.0 3.0 3.0 1.0 1.0 1.0 1.0 7.0 5.0 4.0 3.0 12 10 6.0 5.0 1.0 1.0 1.0 1.0 15 13 9.0 8.0 1.0 1.0 1.0 1.0 18 16 12 11 ns t bbm minimum break?before?make time v is = 3.0 v (figure 3) r l = 300 c l = 35 pf 2.5 3.0 4.5 5.5 2.0 2.0 3.0 3.0 1.0 1.0 1.0 1.0 12 11 6.0 5.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 ns *typical characteristics are at 25 c. typical @ 25, v cc = 5.0 v c in c no or c nc c com c (on) maximum input capacitance, select input analog i/o (switch off) common i/o (switch off) feedthrough (switch on) 8.0 10 10 20 pf additional application characteristics (voltages referenced to gnd unless noted) v cc typical symbol parameter condition (v) 25 c unit bw maximum on?channel ?3.0 db bandwidth or minimum frequency response (figure 10) v in = 0 dbm v in centered between v cc and gnd (figure 6) 3.0 4.5 5.5 145 170 175 mhz v onl maximum feedthrough on loss v in = 0 dbm @ 100 khz to 50 mhz v in centered between v cc and gnd (figure 6) 3.0 4.5 5.5 2.0 2.0 2.0 db v iso off?channel isolation (figure 9) f = 100 khz; v is = 1.0 v rms v in centered between v cc and gnd (figure 6) 3.0 4.5 5.5 93 93 93 db q charge injection select input to common i/o (figure 14) v in = v cc to gnd, f is = 20 khz t r = t f = 3.0 ns r is = 0 , c l = 1000 pf q = c l * v out (figure 7) 3.0 5.5 1.5 3.0 pc thd total harmonic distortion thd + noise (figure 13) f is = 20 hz to 100 khz, r l = rgen = 600 , c l = 50 pf v is = 5.0 v pp sine wave 5.5 0.1 % vct channel?to?channel crosstalk f = 100 khz; v is = 1.0 v rms v in centered between v cc and gnd (figure 6) 5.5 3.0 90 90 db
nlas325 http://onsemi.com 5 10 % 10% 50% 50% output input 0 v v oh v ol 35 pf v cc output dut open i nput 50% 90% 90% 50% output input 0 v 35 pf output open input input gnd 90% output gnd switch select pin 35 pf output dut figure 3. t bbm (time break?before?make) 300 v cc v cc 90% of v oh figure 4. t on /t off t on t off v oh v cc figure 5. t on /t off t on t off v cc 300 0.1 f t bmm v out v ol v out dut v cc 300 v out 0.1 f
nlas325 http://onsemi.com 6 transmitted output dut input reference channel switch control/s test socket is normalized. off isolation is measured across an off channel. on loss is the bandwidth of an on switch. v iso , bandwidth and v onl are independent of the input signal direction. v iso = off channel isolation = 20 log for v in at 100 khz v onl = on channel loss = 20 log for v in at 100 khz to 50 mhz bandwidth (bw) = the frequency 3.0 db below v onl v ct = use v iso setup and test to all other switch analog input/outputs terminated with 50 50 50 generator figure 6. off channel isolation/on channel loss (bw)/crosstalk (on channel to off channel)/v onl 50 v out v in v out v in on off off output dut open v out v cc gnd output v in c l figure 7. charge injection: (q) v in ?55 ?20 leakage (na) figure 8. switch leakage vs. temperature 1 i no(off) temperature ( c) 0.01 25 0.001 0.1 70 85 125 i com(on) i com(off) v cc = 5.0 v 10 100
nlas325 http://onsemi.com 7 figure 9. off?channel isolation figure 10. typical bandwidth and phase shift 1 0.1 0.01 3.0 30 2.5 4.5 35 figure 11. t on and t off vs. v cc at 25 c v cc (volts) figure 12. t on and t off vs. temp temperature ( c) time (ns) time (ns) figure 13. total harmonic distortion plus noise vs. frequency frequency (khz) figure 14. charge injection vs. com voltage v com (v) thd + noise (%) q (pc) 10 1 100 ?55 25 12 5 ?40 20 15 25 0 034 2 15 t on v cc = 3 v v cc = 5 v 2.5 2.0 1.5 1.0 0.5 0 ?0.5 v inpp = 5.0 v v cc = 5.5 v v inpp = 3.0 v v cc = 3.6 v 10 5 t off t on (ns) t off (ns) v cc = 4.5 v 3.5 4 30 20 15 25 0 10 5 85 0.01 10 1 0.1 (db) ?100 0 off isolation frequency (mhz) 100 200 ?80 ?60 ?40 ?20 v cc = 5.0 v t a = 25 c 0.01 10 1 0.1 100 300 frequency (mhz) phase ( ) bandwidth (on?response) phase shift v cc = 5.0 v t a = 25 c ?5 ?15 ?35 ?10 ?20 ?30 ?25 0 +5 +10 +15 (db) 2.0 4.0 6.0 10.0 0 1.0 3.0 5.0 7.0 9.0 8.0
nlas325 http://onsemi.com 8 0 5 10 15 20 25 30 35 40 45 50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 25 c ?55 c 85 c 125 c 85 c ?55 c 125 c 0 10 20 30 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 25 c ?55 c 85 c 25 c 125 c 0 10 20 30 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3 .0 0.0 2.0 1.0 3.0 4.0 5.0 6 .0 temperature ( c) figure 15. i cc vs. temp, v cc = 3.0 v and 5.0 v i cc (na) 80 100 60 40 20 0 figure 16. r on vs. v cc, temp = 25 c v is (vdc) figure 17. r on vs temp, v cc = 2.0 v r on ( ) r on ( ) figure 18. r on vs. temp, v cc = 2.5 v v is (vdc) figure 19. r on vs. temp, v cc = 3.0 v v is (vdc) r on ( ) r on ( ) ?40 60 80 20 0 100 ?20 120 v cc = 2.0 v v cc = 2.5 v v cc = 3.0 v v cc = 4.0 v v cc = 5.5 v v cc = 3.0 v v cc = 5.0 v 10 1 0.1 100 0.01 0.001 0.0001 0.00001 figure 20. r on vs. temp, v cc = 4.5 v v is (vdc) 0 5 10 15 20 25 30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4 .5 r on ( ) v is (vdc) 25 c ?55 c 125 c 85 c
nlas325 http://onsemi.com 9 figure 21. r on vs. temp, v cc = 5.0 v figure 22. r on vs. temp, v cc = 5.5 v 20 15 r on ( ) 10 25 v is (vdc) 5 0 0.0 2.0 1.5 1.0 0.5 2.5 3.0 3.5 4.0 4.5 5.0 25 c 85 c 125 c ?55 c 20 15 r on ( ) 10 25 v is (vdc) 5 0 0.0 2.0 1.5 1.0 0.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 25 c 85 c 125 c ?55 c ordering information device order number device nomenclature package type tape and reel size ? circuit indicator technology device function package suffix NLAS325US nl as 325 us us8 178 mm (7 ) 3000 unit NLAS325USg nl as 325 usg us8 (pb?free) 178 mm (7 ) 3000 unit ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
nlas325 http://onsemi.com 10 package dimensions us8 us suffix case 493?02 issue b dim a min max min max inches 1.90 2.10 0.075 0.083 millimeters b 2.20 2.40 0.087 0.094 c 0.60 0.90 0.024 0.035 d 0.17 0.25 0.007 0.010 f 0.20 0.35 0.008 0.014 g 0.50 bsc 0.020 bsc h 0.40 ref 0.016 ref j 0.10 0.18 0.004 0.007 k 0.00 0.10 0.000 0.004 l 3.00 3.20 0.118 0.126 m 0 6 0 6 n 5 10 5 10 p 0.23 0.34 0.010 0.013 r 0.23 0.33 0.009 0.013 s 0.37 0.47 0.015 0.019 u 0.60 0.80 0.024 0.031 v 0.12 bsc 0.005 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeters. 3. dimension ?a? does not include mold flash, protrusion or gate burr. mold flash. protrusion and gate burr shall not exceed 0.140 mm (0.0055?) per side. 4. dimension ?b? does not include inter?lead flash or protrusion. inter?lead flash and protrusion shall not e3xceed 0.140 (0.0055?) per side. 5. lead finish is solder plating with thickness of 0.0076?0.0203 mm. (300?800 ?). 6. all tolerance unless otherwise specified 0.0508 (0.0002 ?). l b a p g 4 1 5 8 c k d seating j s r u detail e v f h n r 0.10 typ m ?y? ?x? ?t? detail e t m 0.10 (0.004) xy t 0.10 (0.004) plane mm inches scale 8:1 3.8 0.15 0.50 0.0197 1.0 0.0394 0.30 0.012 1.8 0.07 soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, r epresentation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 nlas325/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
|
